When designing oscillators, tradeoffs are often made between area, power consumption and accuracy. Accuracy can be affected by the absolute calibrated accuracy at the time of calibration and by frequency drift due to temperature and voltage variation. High accuracy oscillators are available. Such devices, however, use a high amount of power and have a production cost. Additionally, such high accuracy oscillators are vulnerable to frequency drift due to assumptions about initial characterization made during production calibration.
A digital frequency locked loop (DFLL) combined with an accurate reference oscillator and a calibrateable, low power oscillator can overcome the power consumption issue because the reference oscillator need only be turned on at regular intervals. A DFLL tries to maintain a certain frequency of a target oscillator based on a reference oscillator to minimize the instantaneous frequency error of the target oscillator. A limiting factor, however, is the calibration step size of the target oscillator, which can cause frequency error even when the DFLL operates correctly. Additionally, a DFLL combined with an accurate reference oscillator does not address frequency drift due to temperature and voltage variation, or assumptions about initial device characterization made during production calibration.